1. Field of the Invention
The present invention relates to a differential amplifier circuit for supplying a certain voltage, and in particular, to a technique of improving a power supply rejection ratio of the differential amplifier circuit.
2. Description of Related Art
Known differential amplifier circuits include a so-called regulator circuit designed to compare a certain voltage derived from a power supply voltage with a reference voltage, and supply a desired constant voltage (output voltage) in accordance with a result of the comparison. Such a regulator circuit is disclosed, for example, in Japanese Patent Application Publication (Kokai) No. 2003-177829 and Japanese Patent No. 4054804 (or WO 2003/091817). In this regulator circuit, the reference voltage is supplied to the gate of one of paired differential input elements in an input circuit, and the certain voltage derived from the power supply voltage is supplied to the gate of the other of the differential input elements. Here, the certain voltage derived from the power supply voltage is a feedback output voltage negatively fed back from a power supply through an output element and a voltage divider resistor.
In the regulator circuit disclosed in Japanese Patent Application Kokai No. 2003-177829, a phase compensation circuit with a resistor and a capacitor is disposed between the other of the differential input elements of the input circuit, and the output element for supplying a constant regulator voltage (output voltage). The phase compensation circuit can suppress change of the regulator voltage that would be caused by the characteristics of the regulator circuit itself.
A power supply voltage supplied to the regulator circuit is not always constant, but it changes with a certain cycle. This results in instability of the regulator voltage, i.e., instability of the output voltage. Specifically, a noise signal of the power supply voltage reduces the power supply rejection ratio (PSSR) of the regulator circuit. One reason therefore is as follows. The certain voltage is supplied from the power supply to the gate of the other of the paired differential input elements of the input circuit after passing through the output element and the voltage divider resistor. This creates a delay due to the presence of a path (feedback line) for connecting the other of the paired differential input elements to the power supply through the output element and the voltage divider resistor. There is another reason. A certain time interval is required between supplying of the certain voltage to the gate of the other of the paired differential input elements and turning on of an active load element connected to the paired differential input elements. This creates a delay between turning on of the differential input elements and turning on of the active load element. These delays may be suppressed by increasing current flowing in the paired differential input elements to enhance the operation of the paired differential input elements. This, however, increases consumption current of the regulator circuit.
The regulator circuit disclosed in Japanese Patent No. 4054804 (WO 2003/091817) suggests a solution to the above-mentioned problems. In this regulator circuit, the gate of the other of the paired differential input elements of an input circuit receives not only a feedback output voltage negatively fed back through a voltage divider resistor, but also a cancel signal from a cancel signal generating circuit. The cancel signal is produced on the basis of the change of a power supply voltage. The cancel signal generating circuit prevents the above-described delays even when the change of the power supply voltage occurs. Thus, the regulator voltage can be supplied stably despite the change of the power supply voltage.